/*====设计块: Ripplecounter. v ====*/
module Ripplecounter (
output [3:0]Q,
input CP, CLR_n
);
//实例引用分频器子模块
_2Divider1 FF0 (Q[0],CP,CLR_n);
_2Divider1 FF1 (Q[1],Q[0],CLR_n);
_2Divider1 FF2 (Q[2],Q[1],CLR_n);
_2Divider1 FF3 (Q[3],Q[2],CLR_n);
endmodule

module _2Divider1( //分频器子模块
output reg Q,
input CP, Rd_n
);
always @(posedge CP, negedge Rd_n)
       if(~Rd_n) Q<=1'b0;
       else Q<=~Q;

endmodule